(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of avoiding contamination in copper metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
Copper metallization has become a future trend in integrated circuit manufacturing. However, copper contamination of the intermetal dielectric layer is a problem. Copper is a very dangerous contaminant and diffuses very quickly into silicon oxide, the most common material for interlevel dielectric (ILD) and intermetal dielectric (IMD). The application of a barrier layer underlying copper has effectively prevented the copper from making contact to the ILD or IMD layers during metallization. However, exposure of the IMD and ILD layers to copper during etching, chemical mechanical polishing (CMP), cleaning, and other processes is inevitable. This poses a threat for copper contamination control.
For example, when a copper layer 24 and barrier layer 22 over an oxide layer 14 are patterned, as shown in FIG. 1, copper ions 25 will penetrate the oxide layer 14. Likewise, when a damascene or dual damascene process is used, as shown in FIG. 2, the copper 26 is typically polished using chemical mechanical polishing (CMP). Some of the copper may "smear" 27 onto the oxide 14 causing contamination. It is desired to prevent copper contamination during processing, including etching and CMP.
A number of patents address the damascene process. U.S. Pat. No. 5,451,551 to Krishnan et al teaches a method of forming a titanium tungsten cap over copper and polishing away the excess capping layer. U.S. Pat. No. 5,470,789 to Misawa shows a titanium nitride layer that is buff-abraded. U.S. Pat. No. 5,693,563 to Teong shows a barrier layer for copper, but the copper metallization is not recessed. U.S. Pat. No. 5,744,376 to Chan et al discloses a capping layer over a non-recessed copper metallization. U.S. Pat. No. 5,818,110 to Cronin shows a damascene process with an etch stop layer over metal plugs.
Other patents teach etching of metal layers. U.S. Pat. No. 5,766,974 to Sardella et al shows a SiON etch stop layer under a metal layer. U.S. Pat. No. 5,578,166 to Hirota teaches a refractory metal barrier in copper etching, but no barrier over the oxide layer. U.S. Pat. No. 5,240,559 to Ishida, U.S. Pat. No. 5,200,032 to Shinohara and U.S. Pat. No. 5,591,302 to Shinohara et al teach various RIE methods for copper, but without barrier layers over the oxide. U.S. Pat. No. 5,827,426 to Kamide et al disclose a 2-step etching of aluminum lines. U.S. Pat. No. 5,783,483 to Gardner teaches a metal oxide etch barrier under a metal layer. Gardner's barrier has a high dielectric constant and nonuniformity problems.